This invention relates to the field of integrated circuit memory cells, particularly memory cells employing antifuse layers.
Three-dimensional memories, including memories with cells having antifuse layers, have been described in several prior art publications. Such publications include U.S. Pat. Nos. 5,835,396; 6,034,882; and PCT/US01/13575, filed Apr. 25, 2001.
In the process of fabricating three-dimensional arrays, improvements to the memory cells have been discovered that enhance the cells performance and manufacturability.
A memory cell is described having first and second spaced-apart conductors generally fabricated one above the other and preferably at right angles to each other. First and second heavily doped regions, doped with a first conductivity type dopant, are disposed between the conductors with one of the regions coupled to the first conductor. In an alternate embodiment, one of the heavily doped regions can be a conductor. An antifuse region such as a silicon dioxide layer is disposed between the first and second heavily doped regions. A third region of a second conductivity type is in contact with the second doped region and electrically coupled to the second conductor. The junction between the second and third regions form a diode which is part of the memory cell. In one embodiment, at least one of the first and second doped regions is dedicated to a single memory cell and does not extend to, or communicate with, other cells. In a currently preferred embodiment, the first conductivity type dopant is a P type dopant.